For computer memory to be accessed, a physical address of a memory unit needs to be provided. Generally, a central processing unit (CPU) supports paging memory management. Under a condition of paging memory management, an address generated by the CPU is called a linear address or a virtual address, and the computer memory can be accessed only after the linear address is converted into a physical address by using a page table stored in a TLB.
When the computer memory is accessed by using a set associative translation lookaside buffer (TLB) structure, different TLBs may be simultaneously indexed according to different parts of the linear address. For example, for a conversion from a linear address in which a 4K page is stored to a physical address and a conversion from a linear address in which a 2M page is stored to a physical address, each TLB can determine a set associative group; in different indexed groups, a TLB table entry in a group that matches the linear address is determined, and the linear address is converted into a physical address according to the TLB table entry. It should be noted that a quantity of used types of page sizes is the same as a quantity of TLBs, and therefore, all TLBs need to be simultaneously queried when an address conversion is performed.
In addition, when a process only uses one type of page, which bits of a linear address that are to be used to index a set associative TLB are selected according to a page size used by the running process, a TLB table entry in a group of the set associative TLB is determined, and the linear address is converted into a physical address according to the TLB table entry.
However, when a physical address is obtained by using the prior art, multiple TLBs need to be simultaneously queried, which results in relatively high power consumption; or it is required that each process be restricted to using only one type of page, which leads to inflexibility.